信号无法在VHDL中初始化为整数值

entity Example is
    port (
        clk : in std_logic;
        reset : in std_logic;
        data_in : in std_logic_vector(7 downto 0);
        data_out : out std_logic_vector(7 downto 0)
    );
end entity Example;

architecture Behavioral of Example is
    signal my_signal : std_logic_vector(7 downto 0);
begin
    process(clk, reset)
    begin
        if reset = '1' then
            my_signal <= (others => '0'); -- 初始化为全0
        elsif rising_edge(clk) then
            my_signal <= data_in; -- 根据输入数据更新信号值
        end if;
    end process;

    data_out <= my_signal; -- 输出信号值
end architecture Behavioral;