如何从VHDL中的rom_type读取数据？

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity rom_example is
    Port ( clk : in STD_LOGIC;
           addr : in STD_LOGIC_VECTOR (3 downto 0);
           data : out STD_LOGIC_VECTOR (7 downto 0));
end rom_example;

architecture Behavioral of rom_example is
    type rom_type is array (0 to 15) of std_logic_vector(7 downto 0);
    signal my_rom : rom_type := (
        "00000001", "00000010", "00000100", "00001000",
        "00010000", "00100000", "01000000", "10000000",
        "00000000", "00000000", "00000000", "00000000",
        "00000000", "00000000", "00000000", "00000000"
    );
begin
    process(clk)
    begin
        if rising_edge(clk) then
            data <= my_rom(to_integer(unsigned(addr)));
        end if;
    end process;
end Behavioral;