如何在系统verilog中使用Enum中的算术表达式？

typedef enum logic [3:0] {
    ADD = 4'b0000,
    SUB = 4'b0001,
    MUL = 4'b0010,
    DIV = 4'b0011
} Operation;

typedef struct {
    Operation op;
    logic [7:0] value1;
    logic [7:0] value2;
} ArithmeticExpression;

module ArithmeticModule;
    ArithmeticExpression expr;
    
    always_comb begin
        case (expr.op)
            ADD: expr.value1 = expr.value1 + expr.value2;
            SUB: expr.value1 = expr.value1 - expr.value2;
            MUL: expr.value1 = expr.value1 * expr.value2;
            DIV: expr.value1 = expr.value1 / expr.value2;
            default: expr.value1 = 0;
        endcase
    end
    
    // Other module logic
    
endmodule