如何在VHDL中从file变量中取回文件名字符串？

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use STD.TEXTIO.ALL;

entity FileReader is
    Generic (FILENAME : STRING);
    Port (clk : in STD_LOGIC);
end FileReader;

architecture Behavioral of FileReader is
    file dataFile : TEXT open READ_MODE is FILENAME;
    variable line : LINE;
begin
    process(clk)
    begin
        if rising_edge(clk) then
            if not endfile(dataFile) then
                readline(dataFile, line);
                -- 处理读取到的行数据
            end if;
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use STD.TEXTIO.ALL;

entity Testbench is
end Testbench;

architecture sim of Testbench is
    signal clk : STD_LOGIC := '0';
    constant FILENAME : STRING := "data.txt"; -- 设置文件名
begin
    uut : FileReader generic map(FILENAME => FILENAME)
                     port map(clk => clk);

    clk_process : process
    begin
        clk <= not clk;
        wait for 10 ns;
    end process clk_process;

    stimulus : process
    begin
        -- 启动测试平台的其他部分
        wait;
    end process stimulus;
end sim;