如何在VHDL中将整数数组指定为泛型？

entity my_entity is
  generic (
    type integer_array_t is array (natural range <>) of integer;
    constant my_array : integer_array_t := (1, 2, 3)
  );
end entity my_entity;

architecture rtl of my_entity is
  signal my_signal : integer_array_t(my_array'range);
begin
  -- 使用my_signal和my_array进行操作
end architecture rtl;

entity my_top_entity is
end entity my_top_entity;

architecture rtl of my_top_entity is
  signal my_signal : integer_array_t(1 to 3);
begin
  my_instance : my_entity
    generic map (
      my_array => (1, 2, 3)
    )
    port map (
      -- 端口映射
    );
end architecture rtl;