用Case语句实现JK触发器的VHDL程序

library ieee;
use ieee.std_logic_1164.all;

entity jk_trigger is
    port (
        J, K, CLK: in std_logic;
        Q, Qbar: out std_logic
    );
end jk_trigger;

architecture behavior of jk_trigger is
begin
    process (CLK)
    begin
        if rising_edge(CLK) then
            case (J, K) is
                when ('1', '0') =>
                    Q <= '1';
                    Qbar <= '0';
                when ('0', '1') =>
                    Q <= '0';
                    Qbar <= '1';
                when ('1', '1') =>
                    Q <= not Q;
                    Qbar <= not Qbar;
                when others =>
                    null;
            end case;
        end if;
    end process;
end behavior;