用VHDL语言实现随机数发生器

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity RandomNumberGenerator is
    generic (
        WIDTH : positive := 32
    );
    port (
        clk : in std_logic;
        rst : in std_logic;
        random_number : out std_logic_vector(WIDTH-1 downto 0)
    );
end entity RandomNumberGenerator;

architecture Behavioral of RandomNumberGenerator is
    signal seed : unsigned(WIDTH-1 downto 0);
begin
    process(clk, rst)
    begin
        if rst = '1' then
            seed <= (others => '0');
        elsif rising_edge(clk) then
            seed <= seed + 1;
        end if;
    end process;

    random_number <= std_logic_vector(seed);
end architecture Behavioral;