用vhdl实现100 1Hz ~1 1Hz码的时钟分频器

library ieee;
use ieee.std_logic_1164.all;

entity ClockDivider is
    port (
        clk_in : in std_logic;
        clk_out : out std_logic
    );
end entity ClockDivider;

architecture Behavioral of ClockDivider is
    signal counter : integer range 0 to 99 := 0;
    signal clk_out_internal : std_logic := '0';
begin
    process (clk_in)
    begin
        if rising_edge(clk_in) then
            counter <= counter + 1;
            if counter = 99 then
                counter <= 0;
                clk_out_internal <= not clk_out_internal;
            end if;
        end if;
    end process;

    clk_out <= clk_out_internal;
end architecture Behavioral;