我的顶级模特:
module top (G1, Y1, R1, G2, Y2, R2, BT1, BT2, clk, rst);
input BT1, BT2, clk, rst;
output G1, Y1, R1, G2, Y2, R2;
wire En1, En2, En3, CNT_RES, FF_RES, TC_30, TC_5, GE_15, B1, B2, request;
Controll_Unit c1(G1, Y1, R1, G2, Y2, R2, CNT_RES, FF_RES, B1, B2, BT1, BT2, clk, rst, En1, En2, En