vhdl中的4位比较器问题

entity Comparator is
    port (
        A, B: in std_logic_vector(3 downto 0);
        Greater, Equal, Less: out std_logic
    );
end Comparator;

architecture Behavioral of Comparator is
begin
    process(A, B)
    begin
        if A > B then
            Greater <= '1';
            Equal <= '0';
            Less <= '0';
        elsif A = B then
            Greater <= '0';
            Equal <= '1';
            Less <= '0';
        else
            Greater <= '0';
            Equal <= '0';
            Less <= '1';
        end if;
    end process;
end Behavioral;