将一个数字提升到在VHDL中变化的幂

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Power is
    generic (
        N : positive := 8  -- 数字的位宽
    );
    port (
        clk : in std_logic;
        reset : in std_logic;
        num : in unsigned(N-1 downto 0);
        power : out unsigned(N-1 downto 0)
    );
end entity Power;

architecture Behavioral of Power is
begin
    process(clk, reset)
        variable temp : unsigned(N-1 downto 0);
    begin
        if reset = '1' then
            power <= (others => '0');  -- 复位时输出0
        elsif rising_edge(clk) then
            temp := num;
            power <= (others => '1');  -- 幂的初始值为1
            for i in 1 to N-1 loop
                power <= power * temp;  -- 通过连续乘法实现幂运算
            end loop;
        end if;
    end process;
end architecture Behavioral;