无法将std_logic添加到未签名

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity example is
  port (
    signal1 : in std_logic;
    signal2 : in unsigned(7 downto 0);
    result : out unsigned(7 downto 0)
  );
end entity example;

architecture rtl of example is
begin
  process(signal1, signal2)
  begin
    if signal1 = '1' then
      result <= signal2 + to_unsigned(1, result'length);
    else
      result <= signal2;
    end if;
  end process;
end architecture rtl;