module ade(
clk,x,y,q
);
input clk;
input [7:0]x,y;
output [15:0]q;
reg [15:0]q;
parameter s0=0,s1=1,s2=2;
reg [2:0]count=0;
reg [1:0]state=0;
reg [15:0]p1,t;
reg [7:0]y_reg;
always @ (posedge clk)
begin
case(state)
s0:
begin
y_reg<=y;
state<=s1;
count<=0;
p1<=0;
t<={{8{x[7]}},x};
end
s1:
begin
if(count==7)
begin
state<=s2;
end
else
begin
if(y_reg[0]==1)
begin
p1<=p1+t;
y_reg<=y_reg>>1;
t<=t<<1;
count<=count+1;
state<=s1;
end
else
begin
p1<=p1;
y_reg<=y_reg>>1;
t<=t<<1;
count<=count+1;
state<=s1;
end
end
end
s2:
begin
q<=p1;
state<=s0;
end
endcase
end
Endmodule