多路复用通道时出现SystemVerilog错误:实例数组中的非常量索引

module Multiplexer(
  input logic [7:0] inputSignals [0:3],
  input logic [1:0] select,
  output logic [7:0] outputSignal
);

  always_comb begin
    case (select)
      2'b00: outputSignal = inputSignals[0];
      2'b01: outputSignal = inputSignals[1];
      2'b10: outputSignal = inputSignals[2];
      2'b11: outputSignal = inputSignals[3];
    endcase
  end

endmodule

module TopModule;

  Multiplexer mux [
    .inputSignals({8'b0000_0001, 8'b0000_0010, 8'b0000_0100, 8'b0000_1000}),
    .select(select),
    .outputSignal(output)
  ];

  logic [1:0] select;
  logic [7:0] output;

  // 其他代码

endmodule

module TopModule;

  logic [7:0] inputSignal0;
  logic [7:0] inputSignal1;
  logic [7:0] inputSignal2;
  logic [7:0] inputSignal3;
  logic [1:0] select;
  logic [7:0] output;

  Multiplexer mux (
    .inputSignals({inputSignal0, inputSignal1, inputSignal2, inputSignal3}),
    .select(select),
    .outputSignal(output)
  );

  // 其他代码

endmodule