如何在Verilog代码中给出输入矩阵？

module matrix_multiplier (
  input [7:0] matrix_A [0:3][0:3],
  input [7:0] matrix_B [0:3][0:3],
  output [15:0] matrix_C [0:3][0:3]
);

  reg [15:0] temp [0:3][0:3];

  // 矩阵乘法计算
  generate
    genvar i, j, k;
    for (i = 0; i < 4; i = i + 1) begin : ROW
      for (j = 0; j < 4; j = j + 1) begin : COL
        always @(*) begin
          temp[i][j] = 0;
          for (k = 0; k < 4; k = k + 1) begin : MUL
            temp[i][j] = temp[i][j] + matrix_A[i][k] * matrix_B[k][j];
          end
        end
      end
    end
  endgenerate

  // 输出结果
  assign matrix_C = temp;

endmodule