Flash memories，Detlev Richter<1>

休了个长假，离正式上班还有几天，先简单更新，进行功课温习和预习。

赶上2月最后一天，希望新年大家都不忘初心，加油再加油~~

学习springer Detlev Richter的“Flash memories， Economic Principles of Performance, Cost and Reliability Optimization”，先跳过NOR flash（关于NOR相关的，我之前也分享过很过，以后慢慢学习、分享），学习从2.4.4开始的NAND flash相关章节。

图2.48是NAND的逻辑结构示意图

图2.49给出32 cell的版图布局和逻辑结构的对应关系。

2.4.4.1 NAND Read Operation and Sensing Principles读操作和Sense原理

图2.50所示，读操作时，WL固定为0V，擦除的cell有电流流过，编程cell没有电流流过。

除了选中cell的栅端加0V，其他cell的栅端加PASS电压VRD_PASS，如图2.51所示

2.4.4.2 NAND Program Operation: Program Inhibit Concept编程操作之编程禁止

NAND阵列的cell的阈值漂移是基于FN效应，两个优点：linearity between the program voltage and the cell Vth and the very low program current required to charge the cell，一是编程电压和阈值电压的线性关系，二是，编程电流小。

编程操作所需的编程脉冲电压通过精确的WL电压控制电路实现：

Gate Stepping, gate voltage is increased step by step, drain and source are tied to ground.

对于编程禁止的cell，像以往老的NAND设计，会在BL上加5V电压，由5V pump导致3.3V下的功耗很大。现在的编程禁止技术叫做Self-Boosted，The capacitive coupling of the pass word line voltage (VPROG_PASS)into the strings to be inhibited are ensured by a correct timing sequence of the string select gates related to the ramp of the pass voltage on all non-selected word lines.

NAND flash对所有WL的时序控制比NOR复杂得多。比如，The timing sequence of string select gate related to the ramp of the pass word line voltages are critical parameters to establish a stable self-boosted inhibit.SSG的时序控制就很重要。

图2.52给出编程操作下的阵列偏置。

而编程操作天生带来两个disturb，如图2.53所示：

如果VPROG_PASS太高，则会带来Program pass voltage disturbance on all neighbor word lines

如果channel potential太低，则会带来Program disturbance on the neighbor bit lines belonging to the target word line

2.4.4.3NAND Erase Operation: Vth Window Margin

擦除一般在well加正高压，所有WL接地。擦除脉宽1~2ms，a long negative high voltage pulse will discharge all programmed cells and shift them back below the zero voltage Vth stage.

看起来擦除操作没那么关键，即使cell被过擦，也不会影响sense操作。This assumption is true for the sensing, but not for the Vth operation window margin definition.可以从图2.54看出，过擦首先引入的问题，the first issue of the NAND erase control is the limited capability of a positive voltage word line sensing. The Vth visibility of the sense operation is limited to a small negative Vth range.

因此，编程阈值分布的Vth_LL很关键，Especially the lower edge influences indirectly the effective coupling of these over erased cells onto the direct neighbor cells in the case this cell is programmed.

NAND擦除操作下将选中block的所有WL接地，非选中float，由此提高array efficiency.

2.4.4.4 NAND: Array and Cell matching

80%的nand的layout都长得像图2.55的左边那样

表2.8给出了NAND阵列结构的小结。

来看一下，2D nand到3D nand，图2.56

2.5 Memory Building Blocks主要构成模块

A memory productis characterized by the ratio between the memory arrays versus the complete diesize- this parameter is defined as cell efficiency. The memory array has to utilize more than 50% of the die size otherwise we consider it as logic device with large embedded memory.阵列效率要大于50%。

2.5.1 Row Decoder: Global and Local X-Decoder

对于NAND来说，The NAND memory segmentation works with long word lines. Single or double sided row decoder circuits are driven by layout considerations to achieve die size optimized fan-outs fitting to the NAND string length.需要考虑ROW DEC的单边或者双边layout

2.5.2 Column Decoder: Global and Local Y-Decoder and Y-Buffer

2.5.2.2 Global Y-decoder for a NAND Array

Shielded bitline sensing方式最初在1994年引用，选择odd和even BL.选择管是厚栅高压管，隔离高压。在NAND擦除操作时，BL通过过孔和BULK连接，follow BULK的电压，在20~24V之间。这里需要高压管去隔离阵列和低压SA、BL控制电路，如图2.61所示的Y-MUX电路。

为了隔离高压引入的4个高压管的管子尺寸以及他们之间的间距很大程度上影响了NAND的真理的规模大小。最新的一个技术有33%的面积上的改善，它将高压隔离功能做到bit line control电路里。

Bit line path在以下情况下只工作在低压：

Read operation-pre-charge of bit lines and sensing of the string current;

Program inhibit control- pre-charging the bit lines with Vcc;

Program control-grounding the bit lines with 0V

2.5.3.2 NAND Page Buffer Circuit-Sense Amplifier for MLC NAND

NAND的sensing原理如图2.65所示：

SLC NAND的sensing电路如图2.66所示：

MLC NAND的sensing电路如图2.67所示：

BL预充到VBL_Clamp=0.7V+Vth，预充完成后，VBL_Clamp接地。The sense current can slowly discharge the bit line potential.同时，SO节点预充到VSO=2.5V.在Sense阶段，VBL_Clamp保持一段时间的VBL_Clamp=0.6V+Vth

2.6.1 Flash Threshold Voltage Window: Margin Setup and Accuracy

如图2.70所示，VTH window可以分为三个区域：

The erased window space- cell distribution below Vth_LH

The programmed window space-cell distribution above Vth_HL

The window space between Vth_LH and Vth_HL, to ensure a distance called read window including the complete reliability margin读窗口

下次学习2.6.2 Principles of Flash Program Algorithm，编程和擦除算法对Vth window的分布影响。

BTW...电子书可私信索取。