RAM latency is CL-tRCD-tRP-tRAS-CMD latency. To understand them, bear in mind that the memory is internally organized as a matrix, where the data are stored at the intersection of the lines and columns.
As previously mentioned, CAS Latency (CL) is the best known memory parameter. It tells us how many clock cycles the memory will delay to return requested data. A memory with CL = 7 will delay seven clock cycles to deliver data, while a memory with CL = 9 will delay nine clock cycles to perform the same operation. Thus, for two memory modules running at the same clock rate, the one with the lowest CL will be faster.
Notice that the clock rate here is the real clock rate under which the memory module is running – i.e., half the rated clock rate. As DDR, DDR2, and DDR3 memories can deliver two data per clock cycle, they are rated with double their real clock rate.
In Figure 1, you can see how CL works. We gave two examples, a memory module with CL = 7 and a memory module with CL = 9. The command in blue would be a “read” command.
A memory with CL = 7 will provide a 22.2% improvement on memory latency over a memory with CL = 9, considering that both are running at the same clock rate.
You can even calculate the time the memory delays until it starts delivering data. The period of each clock cycle can be easily calculated through the formula:
T = 1 / f
Each memory chip is organized internally as a matrix. At the intersection of each row and column we have a small capacitor that is in charge of storing a “0” or a “1” – the data. Inside the memory, the process of accessing the stored data is accomplished by first activating the row then the column where it is located. This activation is done by two control signals called RAS (Row Address Strobe) and CAS (Column Address Strobe). The less time there is between these two signals the better, as the data will be read sooner. RAS to CAS Delay or tRCD measures this time. In Figure 2 we illustrate this, showing a memory with tRCD = 3.
As you can see, RAS to CAS Delay is also the number of clock cycles taken between the “Active” command and a “read” or “write” command.
As with CAS Latency, RAS to CAS Delay works with the memory real clock (which is half of the labeled clock). The lower this parameter, the faster the memory will be, as it will start reading or writing data earlier.
After data is gathered from the memory, a command called Precharge needs to be issued, closing the memory row that was being used and allowing a new row to be activated. RAS Precharge time (tRP) is the time taken between when the Precharge command and the next Active command can be issued. As we learned from the previous page, the Active command starts a read or write cycle
we are giving an example of a memory with tRP = 3.
As with the other parameters, RAS Precharge works with the memory real clock (which is half of the labeled clock). The lower this parameter, the faster the memory will be, as it will issue the Active command earlier.
Adding everything we’ve seen, the time elapsed between issuing the Precharge command and actually getting the data will be tRP + tRCD + CL.
Let’s take a better look at the other two parameters, Active to Precharge Delay (tRAS) and Command Rate (CMD). As with the other parameters, these two parameters work with the memory real clock (which is half of the memory labeled clock). The lower these parameters, the faster the memory will be.