RVA23 profile

RVA23 Profiles

The RVA23 profiles are intended to align implementations of RISC-V 64-bit application processors to allow binary software ecosystems to rely on a large set of guaranteed extensions and a small number of discoverable coarse-grain options. It is explicitly a non-goal of RVA23 to allow more hardware implementation flexibility by supporting only a minimal set of features and a large number of fine-grain extensions.

RVA23 profiles 目的是统一 RISC-V 64 位应用处理器的实现，以便二进制软件生态系统可以依赖于大量的有保证的 extensions 和少量可选的粗粒度选项，而不是通过支持一组最小功能和大量细粒度扩展来提供更多硬件实现灵活性。

Only user-mode (RVA23U64) and supervisor-mode (RVA23S64) profiles are

specified in this family.

本文档只指定了 user-mode（RVA23U64）和 s-mode（RVA23S64）profile.

RVA23U64 Profile

The RVA23U64 profile specifies the ISA features available to user-mode execution environments in 64-bit applications processors. This is the most important profile within the application processor family in terms of the amount of software that targets this profile.

RVA23U64 profile 指定了 64 位应用处理器中用户模式执行环境可用的 ISA 功能，就针对该 profile 的软件数量而言，这是应用处理器家族中最重要的 profile。

RVA23U64 Mandatory Base

RV64I is the mandatory base ISA for RVA23U64 and is little-endian. As per the unprivileged architecture specification, the ECALL instruction causes a requested trap to the execution environment.

RV64I 是 RVA23U64 的强制基本 ISA，也是小端的。根据非特权架构规范，ECALL 指令引发 trap。

RVA23U64 Mandatory Extensions

The following mandatory extensions were present in RVA22U64.

RVA22U64包含以下强制 extensions

• M Integer multiplication and division.
• M 整数乘法和除法
• A Atomic instructions.
• A 原子指令
• F Single-precision floating-point instructions.
• F 单精度浮点指令
• D Double-precision floating-point instructions.
• D 双精度浮点指令
• C Compressed instructions.
• C 压缩指令
• B Bit-manipulation instructions.
• B 位操作指令
• Zicsr CSR instructions. These are implied by presence of F.
• Zicsr CSR 指令。这些指令由 F 的存在隐含。
• Zicntr Base counters and timers.
• Zicntr 基本计数器和定时器
• Zihpm Hardware performance counters.
• Zihpm 硬件性能计数器
• Ziccif Main memory regions with both the cacheability and coherence PMAs must support instruction fetch, and any instruction fetches of naturally aligned power-of-2 sizes up to min(ILEN,XLEN) (i.e., 32 bits for RVA23) are atomic.
• Ziccrsf Main memory regions 带有缓存一致性 PMAs 必须支持指令获取，并且任何自然对齐的 2 的幂大小的指令获取最多到 min(ILEN,XLEN)（例如 RVA23 为 32 位）是原子的。
• Ziccrse Main memory regions with both the cacheability and coherence PMAs must support RsrvEventual.
• Ziccrse 带有缓存一致性 PMAs 的 Main memory regions 必须支持 RsrvEventual。
• Ziccamoa Main memory regions with both the cacheability and coherence PMAs must support all atomics in A.
• Ziccamoa 带有缓存一致性 PMAs 的 Main memory regions 必须支持 A 中的所有原子操作。
• Zicclsm Misaligned loads and stores to main memory regions with both the cacheability and coherence PMAs must be supported.
• Zicclsm 对带有缓存一致性 PMAs 的 Main memory regions 的非对齐加载和存储必须得到支持。
• Za64rs Reservation sets are contiguous, naturally aligned, and a maximum of 64 bytes.
• Za64rs Reservation sets 是连续的、自然对齐的，最大为 64 字节。
• Zihintpause Pause hint.
• Zihintpause 暂停提示
• Zic64b Cache blocks must be 64 bytes in size, naturally aligned in the address space.
• Zic64b 缓存块的大小必须为 64 字节，在地址空间中自然对齐。
• Zicbom Cache-block management instructions.
• Zicbom 缓存块管理指令
• Zicbop Cache-block prefetch instructions.
• Zicbop 缓存块预取指令
• Zicboz Cache-Block Zero Instructions.
• Zicboz 缓存块零指令
• Zfhmin Half-precision floating-point.
• Zfhmin 半精度浮点
• Zkt Data-independent execution latency.
• Zkt 数据独立执行延迟

The following mandatory extensions are new in RVA23U64:

以下强制 extensions 是 RVA23U64 中的新内容

• V Vector extension.
• V 向量扩展

NOTE : V was optional in RVA22U64.

NOTE: V 在 RVA22U64 中是可选的。

• Zvfhmin Vector minimal half-precision floating-point.

Zvfhmin 向量最小半精度浮点

• Zvbb Vector basic bit-manipulation instructions.

Zvbb 向量基本位操作指令

• Zvkt Vector data-independent execution latency.

Zvkt 向量数据独立执行延迟

• Zihintntl Non-temporal locality hints.

Zihintntl 非临时局部性提示

• Zicond Integer conditional operations.

Zicond 整数条件操作

• Zimop may-be-operations.

Zcmop Compressed may-be-operations.

Zcmop 压缩 may-be-operations

• Zcb Additional compressed instructions.

Zcb 额外的压缩指令

• Zfa Additional floating-Point instructions.

Zfa 额外的浮点指令

• Zawrs Wait-on-reservation-set instructions.

Zawrs 等待保留集指令

• Supm Pointer masking, with the execution environment providing a means to select PMLEN=0 and PMLEN=7 at minimum.

Supm 指针掩码化，执行环境提供一种选择至少 PMLEN=0 和 PMLEN=7 的方法

RVA23U64 Optional Extensions

Localized Options

The following localized options are new in RVA23U64:

RVA23U64中新的 localized 选项如下

• Zvkng Vector crypto NIST algorithms with GCM.

Zvkng GCM模式的向量加密 NIST 算法

• Zvksg Vector crypto ShangMi algorithms with GCM.

Zvksg GCM模式的向量加密 ShangMi 算法

NOTE: The scalar crypto extensions Zkn and Zks that were options in

RVA22 are not options in RVA23. The goal is for both hardware and

software vendors to move to use vector crypto, as vectors are now

mandatory and vector crypto is substantially faster than scalar

crypto.

NOTE: scalar crypto extensions Zkn 和 Zks 在RVA22中是可选的但在RVA23中不再是可选的。目的是硬件和软件供应商都使用向量加密，因为向量现在是强制的，而且向量加密比标量加密快得多。

NOTE: We have included only the Zvkng/Zvksg options with GCM to

standardize on a higher performance crypto alternative. Zvbc is listed

as a development option for use in other algorithms, and will become

mandatory. Scalar Zbc is now listed as an expansion option, i.e., it

will probably not become mandatory.

NOTE：我们只包含了带有 GCM 的 Zvkng/Zvksg 选项，以便标准化更高性能的加密替代方案。Zvbc 列为用于其他算法的开发选项，并将成为强制选项。标量 Zbc 现在列为扩展选项，即它可能不会成为强制选项。

Development Options

The following are new development options intended to become mandatory in a future RVA profile.

以下是新的开发选项，在未来的 RVA profile 中成为强制选项

• Zabha Byte and halfword atomic memory operations.

Zabha 字节和半字原子内存操作

• Zacas Compare-and-Swap instructions.

Zacas 比较和交换指令

• Ziccamoc Main memory regions with both the cacheability and coherence PMAs must provide AMOCASQ level PMA support.

Ziccamoc 带有缓存一致性 PMAs 的 Main memory regions 必须提供 AMOCASQ 级别的 PMA 支持

NOTE: Ziccamoc is a new profile-defined extension that ensures Compare and Swap instructions are properly supported in main memory regions. The extension will be added to the PMA section of the privileged architecture manual.

NOTE: Ziccamoc 是一个新的 profile-defined extension，它确保 Compare and Swap 指令在main memory

regions中得到正确支持。该扩展将被添加到特权架构手册的 PMA 部分。

• Zvbc Vector carryless multiplication.

Zvbc 向量无进位乘法

• Zama16b Misaligned loads, stores, and AMOs to main memory regions that do not cross a naturally aligned 16-byte boundary are atomic.

Zama16b 对不跨越自然对齐的 16 字节边界的 main memory regions 的非对齐加载、存储和 AMO 是原子的。

NOTE: Zama16b is a new profile-defined extension that represents the presence of the new Misaligned Atomicity Granule feature added in Sm1p13. The extension will be added to the PMA section of the privileged architecture manual.

NOTE: Zama16b 是一个新的 profile-defined extension，表示在 Sm1p13 中添加的新的 Misaligned Atomicity Granule 功能。该扩展将被添加到特权架构手册的 PMA 部分。

Expansion Options

The following expansion options were also present in RVA22U64:

RVA22U64 中也包含以下 expansion options

• Zfh Scalar half-precision floating-point.

Zfh 标量半精度浮点

The following are new expansion options in RVA23U64:

RVA23U64 中的新的 expansion options 如下

• Zbc Scalar carryless multiply.

Zbc 标量无进位乘法

• Zicfilp Landing Pads.
• Zicfiss Shadow Stack.
• Zvfh Vector half-precision floating-point.

Zvfh 向量半精度浮点

• Zfbfmin Scalar BF16 converts.

Zfbfmin 标量 BF16 转换

• Zvfbfmin Vector BF16 converts.

Zvfbfmin 向量 BF16 转换

• Zvfbfwma Vector BF16 widening mul-add.

Zvfbfwma 向量 BF16 widening mul-add

Transitory Options

There are no transitory options in RVA23U64.

RVA23U64中没有 transitory options

NOTE: Scalar crypto is no longer an option in RVA23U64, though the Zbc

extension has now been exposed as an expansion option.

NOTE：标量加密在 RVA23U64 中不再是一个选项，尽管 Zbc 扩展现在已经暴露为一个 expansion option。

RVA23U64 Recommendations

Implementations are strongly recommended to raise illegal-instruction exceptions on attempts to execute unimplemented opcodes.

强烈建议实现在尝试执行未实现的操作码时引发非法指令异常。

RVA23S64 Profile

The RVA23S64 profile specifies the ISA features available to a

supervisor-mode execution environment in 64-bit applications

processors. RVA23S64 is based on privileged architecture version

1.13.

RVA23S64 profile 指定了 64 位应用处理器中 s-mode 执行环境可用的 ISA 功能。RVA23S64 基于特权架构版本 1.13。

RVA23S64 Mandatory Base

RV64I is the mandatory base ISA for RVA23S64 and is little-endian.

The ECALL instruction operates as per the unprivileged architecture

specification. An ECALL in user mode causes a contained trap to

supervisor mode. An ECALL in supervisor mode causes a requested

trap to the execution environment.

RV64I 是 RVA23S64 的强制基本 ISA，也是小端的。ECALL 指令的操作与非特权架构规范相同。在用户模式下的 ECALL 引发到 s-mode 的 contained trap。在 s-mode 下的 ECALL 引发到执行环境的 requested trap。

RVA23S64 Mandatory Extensions

The following unprivileged extensions are mandatory:

以下 unprivileged extensions 是强制的

• The RVA23S64 mandatory unprivileged extensions include all the mandatory unprivileged extensions in RVA23U64.

RVA23S64 的强制 unprivileged extensions 包括 RVA23U64 中的所有强制的 unprivileged extensions。

• Zifencei Instruction-Fetch Fence.

Zifencei 指令获取栅栏

NOTE: Zifencei is mandated as it is the only standard way to support

instruction-cache coherence in RVA23 application processors. A new

instruction-cache coherence mechanism is under development

(tentatively named Zjid) which might be added as an option in the

future.

NOTE：Zifencei 是强制的，因为它是在 RVA23 应用处理器中支持指令缓存一致性的唯一标准方式。

一种新的指令缓存一致性机制（暂时命名为 Zjid）正在开发，可能会在将来作为选项添加。

The following privileged extensions are mandatory:

以下 privileged extensions 是强制的

• Ss1p13 Supervisor architecture version 1.13.

Ss1p13 s-mode 架构版本 1.13

NOTE: Ss1p13 supersedes Ss1p12.

NOTE：Ss1p13 取代了 Ss1p12。

The following privileged extensions were also mandatory in RVA22S64:

以下 privileged extensions 在 RVA22S64 中也是强制的

• Svbare The satp mode Bare must be supported.

Svbare 必须支持 satp 模式 Bare

• Sv39 Page-based 39-bit virtual-Memory system.

Sv39 基于页的 39 位虚拟内存系统

• Svade Page-fault exceptions are raised when a page is accessed when A bit is clear, or written when D bit is clear.

Svade 当 A 位清除时访问页面或当 D 位清除时写入页面时引发 page-fault

• Ssccptr Main memory regions with both the cacheability and coherence PMAs must support hardware page-table reads.

Ssccptr 带有缓存一致性 PMAs 的 Main memory regions 必须支持硬件页表读取

• Sstvecd stvec.MODE must be capable of holding the value 0 (Direct). When stvec.MODE=Direct, stvec.BASE must be capable of holding any valid four-byte-aligned address.

Sstvecd stvec.MODE 必须能够保存值 0（Direct）。

当 stvec.MODE=Direct 时，stvec.BASE 必须能够保存任何有效的四字节对齐地址。

• Sstvala stval must be written with the faulting virtual address for load, store, and instruction page-fault, access-fault, and misaligned exceptions, and for breakpoint exceptions other than those caused by execution of the EBREAK or C.EBREAK instructions. For virtual-instruction and illegal-instruction exceptions, stval must be written with the faulting instruction.

Sstvala 对于加载、存储和 page-fault、access-fault 和 misaligned 异常，以及除了执行 EBREAK 或 C.EBREAK 指令引起的断点异常之外的断点异常，必须使用故障的虚拟地址写入 stval。

对于虚拟指令和非法指令异常，必须使用故障指令写入 stval。

• Sscounterenw For any hpmcounter that is not read-only zero, the corresponding bit in scounteren must be writable.

Sscounterenw 对于任何不是 read-only zero 的 hpmcounter，scounteren 中的相应位必须可写。

• Svpbmt Page-based memory types

Svpbmt 基于页的内存类型

• Svinval Fine-grained address-translation cache invalidation.

Svinval 细粒度地址转换缓存失效

The following are new mandatory extensions:

以下是新的强制 extensions

• Svnapot NAPOT translation contiguity.

Svnapot NAPOT 转换连续性

NOTE: Svnapot was optional in RVA22.

NOTE：Svnapot 在 RVA22 中是可选的。

• Sstc supervisor-mode timer interrupts.

Sstc s-mode 定时器中断

NOTE: Sstc was optional in RVA22.

NOTE：Sstc 在 RVA22 中是可选的。

• Sscofpmf count overflow and mode-based filtering.

Sscofpmf 计数溢出和基于模式的过滤

• Ssnpm Pointer masking, with senvcfg.PMM and henvcfg.PMM supporting, at minimum, settings PMLEN=0 and PMLEN=7.

Ssnpm 指针掩码化，senvcfg.PMM 和 henvcfg.PMM 至少支持设置 PMLEN=0 和 PMLEN=7。

• Ssu64xl sstatus.UXL must be capable of holding the value 2 (i.e., UXLEN=64 must be supported).

Ssu64xl sstatus.UXL 必须能够保存值 2（例如：必须支持 UXLEN=64）。

NOTE: Ssu64xl was optional in RVA22.

NOTE：Ssu64xl 在 RVA22 中是可选的。

• Sha The augmented hypervisor extension.

Sha 增强的 hypervisor 扩展

NOTE: Sha is a new profile-defined extension that captures the full set of features that are mandated to be supported along with the H extension. There is no change to the features added by including the hypervisor extension in a profile--the new name is solely to simplify the text of the profiles. The definition has been added to the RVA22 profile text, where the hypervisor extension was first added, but will be added to the hypervisor section of the combined ISA manual.

NOTE：Sha 是一个新的 profile-defined extension，它包含了H 扩展必须支持的完整功能集。通过在 profile 中包含 hypervisor extension 添加的功能没有变化——新名称仅用于简化 profile 的文本。该定义已添加到 RVA22 profile 文本中，其中首次添加了 hypervisor 扩展，但将添加到组合 ISA 手册的 hypervisor 部分。

Sha comprises the following extensions:

Sha 包括以下 extensions

H The hypervisor extension.

Ssstateen Supervisor-mode view of the state-enable extension. The

supervisor-mode (sstateen0-3) and hypervisor-mode (hstateen0-3)

state-enable registers must be provided.

Ssstateen s-mode 下的 state-enable extension。必须提供 s-mod（sstateen0-3）和 h-mode（hstateen0-3）state-enable 寄存器。

Shcounterenw For any hpmcounter that is not read-only zero, the corresponding bit in hcounteren must be writable.

Shcounterenw 对于任何不是 read-only zero 的 hpmcounter，hcounteren 中的相应位必须可写。

Shvstvala vstval must be written in all cases described above for stval.

Shvstvala 对于上述所有情况，必须写入 vstval。

Shtvala htval must be written with the faulting guest physical

address in all circumstances permitted by the ISA.

Shtvala 在 ISA 允许的所有情况下，必须使用故障的 guest 物理地址写入 htval。

Shvstvecd vstvec.MODE must be capable of holding the value 0 (Direct).

When vstvec.MODE=Direct, vstvec.BASE must be capable of holding

any valid four-byte-aligned address.

Shvstvecd vstvec.MODE 必须能够保存值 0（Direct）。当 vstvec.MODE=Direct 时，vstvec.BASE 必须能够保存任何有效的四字节对齐地址。

Shvsatpa All translation modes supported in satp must be supported in vsatp.

Shvsatpa stap 支持的所有 translation modes 必须在 vsatp 中支持。

Shgatpa For each supported virtual memory scheme SvNN supported in

satp, the corresponding hgatp SvNNx4 mode must be supported. The

hgatp mode Bare must also be supported.

Shgatpa 对于 satp 中支持的每种虚拟内存方案 SvNN，必须支持相应的 hgatp SvNNx4 模式。hgatp 模式 Bare 也必须支持。

NOTE: The augmented hypervisor extension (exactly equivalent to Sha) was optional in RVA22.

NOTE：增强的 hypervisor extension（与 Sha 完全相同）在 RVA22 中是可选的。

RVA23S64 Optional Extensions

Localized Options

There are no privileged localized options in RVA23S64.

RVA23S64 中没有 privileged localized options。

Development Options

There are no privileged development options in RVA23S64.

RVA23S64 中没有 privileged development options。

Expansion Options

The following privileged expansion options were present in RVA22S64:

RVA22S64 中包含以下 privileged expansion options

• Sv48 Page-based 48-bit virtual-memory system.

Sv48 基于页的 48 位虚拟内存系统

• Sv57 Page-based 57-bit virtual-memory system.

Sv57 基于页的 57 位虚拟内存系统

• Zkr Entropy CSR.

The following are new privileged expansion options in RVA23S64

RVA23S64 中的新的 privileged expansion options 如下

• Svadu Hardware A/D bit updates.

Svadu 硬件 A/D 位更新

• Sdtrig Debug triggers.

Sdtrig 调试触发器

• Ssstrict No non-conforming extensions are present. Attempts to execute unimplemented opcodes or access unimplemented CSRs in the standard or reserved encoding spaces raises an illegal instruction exception that results in a contained trap to the supervisor-mode trap handler.

Ssstrict 不存在不符合规范的扩展。在标准或保留的编码空间中尝试执行未实现的操作码或访问未实现的 CSRs会引发非法指令异常，从而导致 contained trap 到 s-mode 陷阱处理程序。

NOTE: Ssstrict is a new profile-defined extension that restricts the

behavior of reserved encoding spaces. The extension will be added to

the supervisor chapter of the privileged architecture.

NOTE: Ssstrict 是一个新的 profile-defined extension，限制了保留编码空间的行为。该扩展将被添加到特权架构的 s-mode 章节。

NOTE: Ssstrict does not prescribe behavior for the custom encoding

spaces or CSRs.

NOTE: Ssstrict 不规定自定义编码空间或 CSRs 的行为。

NOTE: Ssstrict definition applies to the execution environment claiming to be RVA23-compatible, which must have the hypervisor extension. That execution environment will take a contained trap to supervisor-mode (however that trap is implemented, including, but not limited to, emulation/delegation in the outer execution environment). Ssstrict (and all the other RVA23 mandates and options) do not apply to any guest VMs run by a hypervisor. An RVA23 hypervisor can provide guest VMs that are also RVA23-compatible but with an expanded set of emulated standard instructions. An RVA23 hypervisor can also choose to implement guest VMs that are not RVA23 compatible (e.g., lacking H, or only RVA20).

NOTE：Ssstrict 定义适用于 RVA23 兼容的执行环境，该执行环境必须具有 hypervisor extension。该执行环境将 contained trap 到 s-mode（无论该 trap 如何实现，包括但不限于在外部执行环境中的模拟/委托）。Ssstrict（以及所有其他 RVA23 mandates 和 options）不适用于 hypervisor 运行的任何 guest VMs。RVA23 hypervisor 可以提供也是 RVA23 兼容的 guest VMs，但具有扩展的模拟标准指令集。RVA23 hypervisor 也可以选择实现不兼容 RVA23 的 guest VMs（例如，缺少 H，或仅 RVA20）。

• Svvptc Transitions from invalid to valid PTEs will be visible in bounded time without an explicit memory-management fence.

Svvptc 从无效到有效的 PTEs 的转换将在有界时间内可见，而无需显式的内存管理栅栏。

• Sspm Supervisor-mode pointer masking, with the supervisor execution environment providing a means to select PMLEN=0 and PMLEN=7 at minimum.

Sspm s-mode 指针掩码化，s-mode 执行环境提供一种选择至少 PMLEN=0 和 PMLEN=7 的方法。

Glossary of ISA Extensions

The following unprivileged ISA extensions are defined in Volume I

of the https://github.com/riscv/riscv-isa-manual[RISC-V Instruction Set Manual].

• M Extension for Integer Multiplication and Division
• A Extension for Atomic Instructions
• F Extension for Single-Precision Floating-Point
• D Extension for Double-Precision Floating-Point
• H Hypervisor Extension
• Q Extension for Quad-Precision Floating-Point
• C Extension for Compressed Instructions
• B Extension for Bit Manipulation
• V Extension for Vector Computation
• Zifencei Instruction-Fetch Fence Extension
• Zicsr Extension for Control and Status Register Access
• Zicntr Extension for Basic Performance Counters
• Zihpm Extension for Hardware Performance Counters
• Zihintpause Pause Hint Extension
• Zfh Extension for Half-Precision Floating-Point
• Zfhmin Minimal Extension for Half-Precision Floating-Point
• Zfinx Extension for Single-Precision Floating-Point in x-registers
• Zdinx Extension for Double-Precision Floating-Point in x-registers
• Zhinx Extension for Half-Precision Floating-Point in x-registers
• Zhinxmin Minimal Extension for Half-Precision Floating-Point in x-registers
• Zba Address Computation Extension
• Zbb Bit Manipulation Extension
• Zbc Carryless Multiplication Extension
• Zbs Single-Bit Manipulation Extension
• Zk Standard Scalar Cryptography Extension
• Zkn NIST Cryptography Extension
• Zknd AES Decryption Extension
• Zkne AES Encryption Extension
• Zknh SHA2 Hashing Extension
• Zkr Entropy Source Extension
• Zks ShangMi Cryptography Extension
• Zksed SM4 Block Cypher Extension
• Zksh SM3 Hashing Extension
• Zkt Extension for Data-Independent Execution Latency
• Zicbom Extension for Cache-Block Management
• Zicbop Extension for Cache-Block Prefetching
• Zicboz Extension for Cache-Block Zeroing
• Zawrs Wait-on-reservation-set instructions
• Zacas Extension for Atomic Compare-and-Swap (CAS) instructions
• Zabha Extension for Byte and Halfword Atomic Memory Operations
• Zbkb Extension for Bit Manipulation for Cryptography
• Zbkc Extension for Carryless Multiplication for Cryptography
• Zbkx Crossbar Permutation Extension
• Zvbb - Vector Basic Bit-manipulation
• Zvbc - Vector Carryless Multiplication
• Zvkng - NIST Algorithm Suite with GCM
• Zvksg - ShangMi Algorithm Suite with GCM
• Zvkt - Vector Data-Independent Execution Latency

The following privileged ISA extensions are defined in Volume II of the RISC-V Instruction Set Manual.

• Sv32 Page-based Virtual Memory Extension, 32-bit
• Sv39 Page-based Virtual Memory Extension, 39-bit
• Sv48 Page-based Virtual Memory Extension, 48-bit
• Sv57 Page-based Virtual Memory Extension, 57-bit
• Svpbmt, Page-Based Memory Types
• Svnapot, NAPOT Translation Contiguity
• Svinval, Fine-Grained Address-Translation Cache Invalidation
• Hypervisor Extension
• Sm1p11, Machine Architecture v1.11
• Sm1p12, Machine Architecture v1.12
• Ss1p11, Supervisor Architecture v1.11
• Ss1p12, Supervisor Architecture v1.12
• Ss1p13, Supervisor Architecture v1.13
• Sstc Extension for Supervisor-mode Timer Interrupts
• Sscofpmf Extension for Count Overflow and Mode-Based Filtering
• Smstateen/Ssstateen Extension for State-enable
• Svvptc Obviating Memory-management Instructions after Marking PTEs valid
• Svadu Hardware Updating of A/D Bits

The following extensions have not yet been incorporated into the RISC-V

Instruction Set Manual; the hyperlinks lead to their separate specifications.

• Zve32x Extension for Embedded Vector Computation (32-bit integer)
• Zve32f Extension for Embedded Vector Computation (32-bit integer, 32-bit FP)
• Zve32d Extension for Embedded Vector Computation (32-bit integer, 64-bit FP)
• Zve64x Extension for Embedded Vector Computation (64-bit integer)
• Zve64f Extension for Embedded Vector Computation (64-bit integer, 32-bit FP)
• Zve64d Extension for Embedded Vector Computation (64-bit integer, 64-bit FP)
• Ziccif: Main memory supports instruction fetch with atomicity requirement
• Ziccrse: Main memory supports forward progress on LR/SC sequences
• Ziccamoa: Main memory supports all atomics in A
• Ziccamoc Main memory supports atomics in Zacas
• Zicclsm: Main memory supports misaligned loads/stores
• Zama16b: Misaligned loads, stores, and AMOs to main memory regions that do not cross a naturally aligned 16-byte boundary are atomic.
• Za64rs: Reservation set size of at most 64 bytes
• Za128rs: Reservation set size of at most 128 bytes
• Zic64b: Cache block size is 64 bytes
• Svbare: Bare mode virtual-memory translation supported
• Svade: Raise exceptions on improper A/D bits
• Ssccptr: Main memory supports page table reads
• Sscounterenw: Support writeable enables for any supported counter
• Sstvecd: stvec supports Direct mode
• Sstvala: stval provides all needed values
• Ssu64xl: UXLEN=64 must be supported
• Sha: Augmented hypervisor extension
• Shcounterenw: Support writeable enables for any supported counter
• Shvstvala: vstval provides all needed values
• Shtvala: htval provides all needed values
• Shvstvecd: vstvec supports Direct mode
• Shvsatpa: vsatp supports all modes supported by satp
• Shgatpa: SvNNx4 mode supported for all modes supported by satp, as well as Bare
• Ssstrict: Unimplemented reserved encodings raise illegal instruction exceptions and no non-conforming extension are present

With the help of github Copilot and Gemini 2 flash