问verilog中的位切片

EN

module temp(clk);
  input clk;
  reg i, j;
  reg [23:0] register, select;
  wire [23:0] temp;

  initial 
  begin
      i = 'd1;
      j = 'd1;
  end

  generate
  for(genvar i = 0; i<24; i++)
  begin
      assign temp[i] = select[i] ? $random : register[i]; 
  end
  endgenerate

  always @ (posedge clk)
  begin
      register <= temp;
  end

  always @ *
  begin
      select = (32'hffff_ffff << ((j<<3)+8)) ^ (32'hffff_ffff << (i<<3));
  end
endmodule

bit [7:0] PA, PB;
int loc;

initial begin
  loc = 3;
  PA = PB;                      // Read/Write
  PA[7:4] = 'hA;                // Read/Write of a slice
  PA[loc -:4] = PA[loc+1 +:4];  // Read/Write of a variable slice equivalent to PA[3:0] = PA[7:4];
end

[M -: N]  // negative offset from bit index M, N bit result 
[M +: N]  // positive offset from bit index M, N bit result